Hi Malek,

What we select in the Wizard window defines how the port contents are interpreted, not the actual VHDL type of the port. As I mentioned, the VHDL type itself is still std_logic_vector, but inside the IP the data carried by that vector is interpreted as a signed value.

Yes, the type BIT is synthesized and it is not thrown away. A signal of type BIT simply becomes a single wire or register that can only be 0 or 1.

The real difference between BIT and std_logic is simulation, not hardware. BIT is a two-value type (0 and 1). std_logic is a simulation type with extra values like U, X, and Z. For example, Z is how we model tri-state behavior, which is required to describe and implement bi-directional I/O pins.

Another practical reason we avoid BIT is ecosystem support. Standard packages such as numeric_std only work with std_logic.

I have a question regarding the type of the IP inputs. You said that the inputs of the IP have type Std_Logic_Vector. But, the in the window that shows the details of the IP we have chosen that A and B have type signed!!

Yes. You can use it everywhere within the Architecture section.

Hi Malek,

In VHDL, ‘length is an integer, so when you do math on it, VHDL uses integer arithmetic and simply truncates the result.

For example, if A’length is 7, then A’length/2 becomes 3. It’s basically rounded down. If you want it to be rounded up instead, you can write:

(A’length + 1)/2