Comments for FPGATEK

Comment on FPGA Design Blueprint by Emanuele Cavaliere

Emanuele Cavaliere — Wed, 04 Feb 2026 12:07:12 +0000

Should I want to have hardware at hand to work with ISE I found a 60 euro board on aliexpress Spartan6 LX16 complete with usb blaster JTAG programmer: could it be a reasonable choice?
Regards

Comment on Using IP Cores in the ISE Design Suite by Ahmad Saghafi

Ahmad Saghafi — Wed, 28 Jan 2026 11:54:57 +0000

In reply to Malek Mastafa. Hi Malek, What we select in the Wizard window defines how the port contents are interpreted, not the actual VHDL type of the port. As I mentioned, the VHDL type itself is still std_logic_vector, but inside the IP the data carried by that vector is interpreted as a signed value.

Comment on An Introduction to VHDL Language by Ahmad Saghafi

Ahmad Saghafi — Wed, 28 Jan 2026 10:56:42 +0000

In reply to Stuart O’Reilly.

Yes, the type BIT is synthesized and it is not thrown away. A signal of type BIT simply becomes a single wire or register that can only be 0 or 1.

The real difference between BIT and std_logic is simulation, not hardware. BIT is a two-value type (0 and 1). std_logic is a simulation type with extra values like U, X, and Z. For example, Z is how we model tri-state behavior, which is required to describe and implement bi-directional I/O pins.

Another practical reason we avoid BIT is ecosystem support. Standard packages such as numeric_std only work with std_logic.

Comment on An Introduction to VHDL Language by Stuart O'Reilly

Stuart O'Reilly — Tue, 27 Jan 2026 07:10:47 +0000

at the end of the video you said the type BIT is only used in simulation. Well, if it is in your code, what happens to it when you synthesize your code and build your bit file?….It can’t just get thrown out as that would break your code. Does it get implemented using a byte in h/w BUT acts as a BIT?

Comment on Using IP Cores in the ISE Design Suite by Malek Mastafa

Malek Mastafa — Wed, 14 Jan 2026 21:03:07 +0000

Hi Ahmad,

I have a question regarding the type of the IP inputs. You said that the inputs of the IP have type Std_Logic_Vector. But, the in the window that shows the details of the IP we have chosen that A and B have type signed!!

Comment on Using Generic Feature for Easier Coding by Ahmad Saghafi

Ahmad Saghafi — Mon, 05 Jan 2026 11:36:37 +0000

In reply to Malek Mastafa. Yes. You can use it everywhere within the Architecture section.

Comment on Using Generic Feature for Easier Coding by Malek Mastafa

Malek Mastafa — Sun, 04 Jan 2026 21:22:45 +0000

can you you the generic that you define in the entity in the architecture?

Comment on Describing Sequential Circuits with VHDL by Ahmad Saghafi

Ahmad Saghafi — Mon, 29 Dec 2025 13:53:58 +0000

In reply to Malek Mastafa.

Hi Malek,

In VHDL, ‘length is an integer, so when you do math on it, VHDL uses integer arithmetic and simply truncates the result.

For example, if A’length is 7, then A’length/2 becomes 3. It’s basically rounded down. If you want it to be rounded up instead, you can write:

(A’length + 1)/2

Comment on Describing Sequential Circuits with VHDL by Malek Mastafa

Malek Mastafa — Sun, 28 Dec 2025 22:52:37 +0000

Hi Ahmad. what if ‘length is odd number. what will happen if i divide it by 2

Comment on IF-THEN-ELSE Statement in the Process Section by Ahmad Saghafi

Ahmad Saghafi — Sat, 06 Dec 2025 07:22:47 +0000

In reply to Paul Norman.

Good question. What I explained in this video is about describing combinational circuits inside a process statement. In combinational circuits, any change in an input can cause a change in the output, independent of the other inputs. So the rule is: include all inputs in the sensitivity list.

However, this isn’t what you’ll typically do in practice. Almost all the circuits you describe will be synchronous sequential, meaning they have a clock input and every operation is synchronized with the rising edge of the clock. In that case, the only signal you place in the sensitivity list is the clock itself.

We’ll talk about this in more detail in the upcoming lessons.