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	<link>https://fpgatek.com</link>
	<description>Learn how to implement digital circuits with FPGA from scratch</description>
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	<item>
		<title>FPGA Pin Assignment in UCF File: How to Connect Circuit Ports to FPGA Pins</title>
		<link>https://fpgatek.com/fpga-pin-assignment/</link>
					<comments>https://fpgatek.com/fpga-pin-assignment/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Sat, 06 Dec 2025 14:42:30 +0000</pubDate>
				<category><![CDATA[Miscellaneous Topics]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1978</guid>

					<description><![CDATA[In this article, I want to talk about how to assign the ports of your circuit to the FPGA pins.&#160;This is one of the essential steps you need to take towards the end of the implementation process. I’ll explain this in detail, and by the end, I’ll also provide an example to make the concept [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>In this article, I want to talk about how to assign the ports of your circuit to the FPGA pins.</p><p>This is one of the essential steps you need to take towards the end of the implementation process. I’ll explain this in detail, and by the end, I’ll also provide an example to make the concept clearer for you.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			</item>
		<item>
		<title>Internal RAM Types in Xilinx FPGAs</title>
		<link>https://fpgatek.com/internal-ram-types-in-xilinx-fpgas/</link>
					<comments>https://fpgatek.com/internal-ram-types-in-xilinx-fpgas/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Mon, 01 Dec 2025 15:07:37 +0000</pubDate>
				<category><![CDATA[FPGA Hardware Resources]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Hardware Resources]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1969</guid>

					<description><![CDATA[In this video, I want to talk about two different types of temporary memory, or RAM, that we use in FPGAs.&#160;&#160;After introducing these memory types, I'll discuss when and under what circumstances you should use each type. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>In this video, I want to talk about two different types of <strong>temporary memory</strong>, or <strong>RAM</strong>, that we use in FPGAs.&nbsp;</p><p>After introducing these memory types, I'll discuss when and under what circumstances you should use each type.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			</item>
		<item>
		<title>How to Use IP Cores In Xilinx ISE Design Suite</title>
		<link>https://fpgatek.com/ip-cores-in-xilinx-ise-design-suite/</link>
					<comments>https://fpgatek.com/ip-cores-in-xilinx-ise-design-suite/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Mon, 01 Dec 2025 09:30:07 +0000</pubDate>
				<category><![CDATA[ISE Design Suite]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[ISE]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1947</guid>

					<description><![CDATA[In this video, I want to talk about one of the most important and widely used features in the ISE software.&#160;With this capability, you can significantly speed up the implementation process for your systems and, of course, save on costs. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>In this video, I want to talk about one of the most important and widely used features in the ISE software.</p><p>With this capability, you can significantly speed up the implementation process for your systems and, of course, save on costs.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
			</item>
		<item>
		<title>Building Digital Circuits with VHDL – Part 4</title>
		<link>https://fpgatek.com/if-statement-in-vhdl/</link>
					<comments>https://fpgatek.com/if-statement-in-vhdl/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Tue, 23 Sep 2025 14:05:14 +0000</pubDate>
				<category><![CDATA[VHDL]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1938</guid>

					<description><![CDATA[This is part four of our VHDL tutorial series. Today, we're diving into how to design combinational circuits within the sequential region using the if statement in VHDL.&#160;From previous lessons, you’ll likely remember that every VHDL code is generally composed of two main sections: Entity and Architecture.&#160; [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>This is part four of our VHDL tutorial series. Today, we're diving into how to design <strong>combinational circuits</strong> within the sequential region using the <strong>if</strong> statement in VHDL.</p><p>From <a href="https://fpgatek.com/conditional-signal-assignment-in-vhdl/" target="_blank">previous lessons</a>, you’ll likely remember that every VHDL code is generally composed of two main sections: <strong>Entity </strong>and <strong>Architecture.</strong>&nbsp;</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
			</item>
		<item>
		<title>Circuit Simulation Using ISim in Xilinx ISE Design Suite</title>
		<link>https://fpgatek.com/circuit-simulation-with-isim/</link>
					<comments>https://fpgatek.com/circuit-simulation-with-isim/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Wed, 26 Mar 2025 11:07:14 +0000</pubDate>
				<category><![CDATA[ISE Design Suite]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[ISE]]></category>
		<category><![CDATA[isim]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1908</guid>

					<description><![CDATA[In this article, I’m going to explain how to simulate digital circuits using the ISim software, which is part of the ISE Design Suite.&#160;&#160;ISim is the simulator provided by Xilinx, and if you have the ISE software installed on your computer, this simulator is also installed alongside it. You can use it to simulate your [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>In this article, I’m going to explain how to simulate digital circuits using the <strong>ISim software</strong>, which is part of the <a href="https://fpgatek.com/your-first-project-in-xilinx-ise/" target="_blank" class="" style="outline: none;">ISE Design Suite</a>.&nbsp;</p><p>ISim is the simulator provided by <a href="https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga.html" target="_blank" rel="noopener">Xilinx</a>, and if you have the ISE software installed on your computer, this simulator is also installed alongside it. You can use it to simulate your circuits.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
			</item>
		<item>
		<title>Building Digital Circuits with VHDL &#8211; Part 3</title>
		<link>https://fpgatek.com/conditional-signal-assignment-in-vhdl/</link>
					<comments>https://fpgatek.com/conditional-signal-assignment-in-vhdl/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Sun, 23 Mar 2025 11:54:31 +0000</pubDate>
				<category><![CDATA[VHDL]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=5224</guid>

					<description><![CDATA[This is the third video in our series of VHDL video tutorials, where I’ll be discussing how to design combinational circuits using the conditional signal assignment construct.&#160;If you haven’t watched the first two videos in this series yet, I recommend pausing this video here and checking out those tutorials first. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>This is the third video in our series of VHDL video tutorials, where I’ll be discussing how to design combinational circuits using the <strong>conditional signal assignment</strong> construct.</p><p>If you haven’t watched the first two videos in this series yet, I recommend pausing this video here and checking out those tutorials first.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
			</item>
		<item>
		<title>Get Started With FPGA In 20 Minutes</title>
		<link>https://fpgatek.com/fpga/</link>
					<comments>https://fpgatek.com/fpga/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Thu, 05 Dec 2024 15:23:18 +0000</pubDate>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Article]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=4780</guid>

					<description><![CDATA[In this guide, I’m going to walk you through the world of FPGA, an incredible device for implementing digital systems.&#160;This technology isn’t just another method; it’s a game-changer in how you tackle digital system projects, enhancing what you can do in this exciting field. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element"><p>In this guide, I’m going to walk you through the world of FPGA, an incredible device for implementing digital systems.</p><p>This technology isn’t just another method; it’s a game-changer in how you tackle digital system projects, enhancing what you can do in this exciting field.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
			</item>
		<item>
		<title>Building Digital Circuits with VHDL &#8211; Part 2</title>
		<link>https://fpgatek.com/designing-combinational-circuits-in-vhdl/</link>
					<comments>https://fpgatek.com/designing-combinational-circuits-in-vhdl/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Sun, 17 Nov 2024 13:55:28 +0000</pubDate>
				<category><![CDATA[VHDL]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1612</guid>

					<description><![CDATA[This is the second part of our VHDL tutorial, where I'll show you how to implement combinational circuits.&#160;If you haven’t yet watched the first part, I highly recommend you pause this video right now and go through that one first, since understanding the concepts in this lesson relies heavily on what we covered previously. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element">	<p>This is the second part of our VHDL tutorial, where I'll show you how to implement <strong>combinational circuits.</strong></p><p>If you haven’t yet watched the <a href="https://fpgatek.com/vhdl-coding-for-fpga-part-1/" target="_blank" class="" style="outline: none;">first part</a>, I highly recommend you pause this video right now and go through that one first, since understanding the concepts in this lesson relies heavily on what we covered previously.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			</item>
		<item>
		<title>Building Digital Circuits with VHDL &#8211; Part 1</title>
		<link>https://fpgatek.com/vhdl-coding-for-fpga-part-1/</link>
					<comments>https://fpgatek.com/vhdl-coding-for-fpga-part-1/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Sun, 10 Nov 2024 15:22:06 +0000</pubDate>
				<category><![CDATA[VHDL]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1599</guid>

					<description><![CDATA[In this video, I’ll introduce you to VHDL. In one of our previous videos, you learned some basic information about VHDL.&#160;However, in this video, we’ll dive deeper into VHDL’s structure and the features it offers. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element"><p>In this video, I’ll introduce you to VHDL. In one of our previous videos, you learned some basic information about VHDL.</p><p>However, in this video, we’ll dive deeper into VHDL’s structure and the features it offers.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
			</item>
		<item>
		<title>How to Create Your First Project in Xilinx ISE Design Suite</title>
		<link>https://fpgatek.com/your-first-project-in-xilinx-ise/</link>
					<comments>https://fpgatek.com/your-first-project-in-xilinx-ise/#respond</comments>
		
		<dc:creator><![CDATA[Ahmad Saghafi]]></dc:creator>
		<pubDate>Tue, 05 Nov 2024 10:48:33 +0000</pubDate>
				<category><![CDATA[ISE Design Suite]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[ISE]]></category>
		<category><![CDATA[Video]]></category>
		<guid isPermaLink="false">https://fpgatek.com/?p=1566</guid>

					<description><![CDATA[The last version of the Xilinx ISE Design Suite was released by Xilinx at the end of 2013, and since then, this software hasn't been updated.&#160;However, we still need to learn and work with this software. [&#8230;]]]></description>
										<content:encoded><![CDATA[<div class="thrv_wrapper thrv_text_element"><p>The last version of the Xilinx ISE Design Suite was released by Xilinx at the end of 2013, and since then, this software hasn't been updated.</p><p>However, we still need to learn and work with this software.</p></div> [&#8230;]<span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span><span class="tve-leads-two-step-trigger tl-2step-trigger-0"></span>]]></content:encoded>
					
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			<slash:comments>0</slash:comments>
		
		
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