This is the second part of our VHDL tutorial, where I'll show you how to implement combinational circuits.
If you haven’t yet watched the first part, I highly recommend you pause this video right now and go through that one first, since understanding the concepts in this lesson relies heavily on what we covered previously.
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Let me first remind you about what we discussed in the previous video.
We discussed how logic circuits can be divided into two main categories: combinational and sequential circuits.
With hardware description languages like VHDL, you can describe and implement either type of logic circuit.
In VHDL, you can describe combinational circuits in the Concurrent section, while sequential circuits are described in the Process statement.
In today’s lesson, I’ll focus on designing and describing combinational logic circuits using VHDL.
In the Concurrent section, VHDL provides two signal assignment statements to describe combinational circuits:
One is called Selected Signal Assignment and the other is Conditional Signal Assignment.
In this video, I’ll focus on the Selected Signal Assignment.
The transcript will be added soon...
