If you're a digital designer looking to implement your idea on a field-programmable gate array (FPGA), there are a few things you need to know.
First of all, your idea needs to be expressed in a standard way that existing software design tools can understand. Once you've done that, you can use these tools to transform your idea into data that the FPGA can work with.
Now, one thing to keep in mind is that there's no standalone processor in an FPGA, which means you can't use programming instructions to create a software routine. Instead, you'll need to describe your digital design in a way that's specific to the FPGA.
So, how do you actually describe a digital design for an FPGA? What are the implementation steps you need to take?
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Hardware Description Languages
To describe a digital hardware design, we use Hardware Description Languages (HDL). These languages are specifically designed to describe various logic and digital functions and operations.
The two most widely used and useful HDL languages in the world are VHDL and Verilog. Despite some differences in their syntax and structure, both languages can be used to describe any digital circuit.
For the purposes of this part of the article, we'll focus on VHDL, which stands for Very High-Speed Integrated Circuit Hardware Description Language. Initially developed by the US Department of Defense for electronic projects, VHDL was standardized by the IEEE in 1987 as part of the IEEE 1076 standard.
VHDL Language Structure
Each VHDL code for describing a digital module consists of two parts: Entity and Architecture.
Let's take a look at a digital chip as an example. This chip has two parts that are highlighted:
Input/output ports
Internal digital circuit
Two main parts of any VHDL code and its connection to the circuit.
The Entity section of the VHDL code describes the input/output ports of the digital module. These ports can be defined as input or output and can be 1-bit or multi-bit.
The Architecture section of the code describes the internal digital circuit. This is where we define the logic gates and connections between them that make up the circuit.
Once the internal circuit is defined, we can perform logic operations on the input values that come in through the input ports. The resulting values are then sent out through the output ports.
Implementation of a Full Adder with VHDL
Let's take a look at a simple example to understand how to describe a digital module using the VHDL language. Suppose we want to implement a Full Adder circuit using FPGA.
First, let's take a look at the digital circuit of a Full Adder and its ports. We have three input ports: 'a,' 'b,' and 'Cin.' 'a' and 'b' are the input bits that we want to add together, along with the carry input 'Cin' (which usually comes from the previous stage).
The output ports of the module are 'Sum' and 'Cout.' 'Sum' is the result of adding 'a,' 'b,' and 'Cin,' while 'Cout' is the 'carry out' bit, which tells us whether or not there is a carry from this stage to the next.
The digital circuit of a Full Adder and its ports.
The first step in describing a digital design using VHDL is to define its ports in the Entity section. The Entity section for describing all the ports of the Full Adder will look like the following figure.
The keywords ENTITY and PORT are used to describe the ports, and the ports are specified as either input or output using the IN or OUT keywords.
entity Full_Adder is
Port (
A, B, Cin : in STD_LOGIC;
Sum, Cout : out STD_LOGIC
);
end Full_Adder;
The data type of the ports of this example is defined by the STD_LOGIC type, which specifies the standard values that the port can take. Some of the possible values for a std_logic port include: '0', '1', 'Z' (high impedance), 'U' (Uninitialized), and 'X' (don't care).
After defining the input/output ports of the design in the Entity section, the next step is to describe the internal digital circuitry, which is done in the Architecture section of the VHDL code. The following figure shows the internal circuitry of the Full Adder module.
Every Architecture must have a name, just like an Entity. Then the Architecture must be associated with an Entity. The digital circuitry can be described after the BEGIN keyword. In the following VHDL code, the digital circuitry is described using the XOR and AND keywords.
To assign the result of a logic operation to an output, the '<=' symbol is used. Finally, By placing the Entity and Architecture sections in a VHDL file (with .vhd extension), a complete Full Adder module can be created and used in later stages of the design process.
architecture Behavioral of Full_Adder is begin Sum <= A xor B xor Cin; Cout <= (A and B) or (A and Cin) or (B and Cin); end Behavioral;
Implementation Steps with FPGA
The designer needs to take several steps to implement a digital design with an FPGA. Fortunately, we can use specialized software programs to help us with most of these steps.
In later parts of this article, we'll introduce some of these software programs and show you how to use them to implement your digital design on an FPGA.
To give you an idea of what the implementation process looks like, here's a flowchart that illustrates the major steps involved in designing an FPGA.
The design steps with FPGA in a flowchart.
Design Entry and Compilation
The first step is to enter our design into a design software tool. This means that we need to describe our design in a way that the software can understand.
As we mentioned earlier, we can use hardware description languages like VHDL or Verilog to describe our design. By writing our design in one of these languages, we can define the inputs and outputs of our circuit, describe the internal circuits and connections, and even simulate how the circuit will behave under different conditions.
While software programs used for entering designs can also describe designs schematically, this is not practical for medium to large designs.
Once the design is entered and any syntax errors are checked, it must be compiled. Compiling the hardware description of the design involves converting the HDL description into a set of logic functions.
Functional Simulation
Once we've compiled our VHDL or Verilog code into a set of logic functions, the next step is to perform a functional simulation of our design.
Functional (also known as behavioral) simulation is a way to evaluate the functionality of our design before we actually implement it in hardware. We can use simulation software tools to simulate the logic of our design and test it under different input conditions.
At this stage, we can only simulate the logic of the design because we don't yet know the delay of the gates and paths. This means that the simulation won't take into account the actual physical characteristics of the circuit, such as how long it takes for a signal to propagate through a gate or along a path.
Design Synthesis and Timing Simulation
After verifying the functionality of our design using functional simulation, the next step is to synthesize it. Synthesis is the process of converting a high-level description of the design to a lower-level description that can be implemented in hardware.
This concept is illustrated below by an example. As shown in the figure, a 1-bit Full Adder can be described using the high-level expression "a + b + Cin = Sum.
A lower-level description of the Full Adder can be expressed using logic gates. Since each logic gate is implemented using transistor circuits, a lower-level description of the Full Adder is a transistor circuit, as shown in the figure.
The concept of synthesis in digital implementation
Logic gates can express a lower-level description of the Full Adder. Since each of these logic gates is implemented using transistor circuits, a lower-level description of the Full Adder is a transistor circuit shown in the figure.
Thus, in this figure, a high-level description of the concept of the Full Adder is synthesized in two steps into lower-level descriptions. But synthesis in an FPGA means the implementation of the logical equations and relationships resulting from the compilation step with the help of "available resources" in that FPGA.
In other words, the design tool should be able to implement the hardware description using logical resources that exist in a particular FPGA, such as LUTs, multiplexers, multipliers, etc.
For this purpose, the design tool must be fully aware of the hardware resources in the target FPGA. Therefore, depending on the type of FPGA chosen by the designer, the result of the synthesis step may differ.
In the synthesis stage, the delay of the gates and other hardware resources used in the design are calculated and considered. Therefore, after the synthesis step, the design can again be simulated.
The difference between this simulation, which is called Timing Simulation, and the Functional Simulation, is that the propagation delays of the sources used in the design are also involved in the simulation. Thus, the simulation is closer to what would happen in reality.
However, synthesis in an FPGA refers to implementing the logic functions generated from the compilation step using the 'available hardware resources' within that FPGA.
In other words, the design tool must be capable of implementing the hardware description using the hardware resources present in a specific FPGA, such as LUTs, multiplexers, multipliers, etc.
To achieve this, the design tool needs to be aware of the hardware resources available in the target FPGA. Therefore, the outcome of the synthesis step may vary depending on the type of FPGA selected by the designer.
In the synthesis stage, the delay of the gates and other hardware resources used in the design are calculated and taken into account. Therefore, after the synthesis step, the design can be simulated again.
The difference between this simulation, known as Timing Simulation and Functional Simulation, is that propagation delays of the resources used in the design are also included in the simulation. As a result, the simulation is more accurate and closer to real-world behavior.
Design Placement
The next crucial step in digital design with FPGA is placement. Since the hardware resources in each FPGA are located in specific and fixed positions within the FPGA, it is essential to determine exactly where the resources used in the synthesis phase are located inside the FPGA.
The design software accomplishes this according to various criteria. One of the most significant criteria is to place resources at points within the FPGA that enable them to connect using shorter paths.
Design Routing and Timing Simulation
Routing is another crucial step in implementing the design. In this stage, the design tool employs advanced algorithms to determine the optimal route to connect the resources used in the design.
Since the paths (wires) themselves have delays, we can perform another Timing Simulation of the design at this stage. In this simulation, known as Post-Place and Rout Simulation, not only are the delays of all hardware resources evaluated, but the delays of wires connecting digital resources are also analyzed.
Configuration File Generation and FPGA Configuration
The next step in the design process is to generate a Configuration File. This binary file includes the results of all the design steps in the form of zeros and ones that need to be loaded into the FPGA. The file contains information about which hardware resources are used in the FPGA, how LUTs are programmed, and how the paths are interconnected.
The final step in the design process is to configure (program) the FPGA. We load the binary configuration file into the FPGA using a particular programmer. After loading this file, the FPGA turns into the hardware described by the HDL language.
