Have you recently started coding in VHDL and are now facing various error messages with each piece of code you write?
Are these messages confusing, leaving you unsure how to fix them?
This article will cover 10 common VHDL coding errors. For each error, I'll explain why it happens, describe the error message you'll see, and show you how to resolve it.
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Understanding VHDL Coding Errors
The first step after writing VHDL code is to check for coding errors. You can do this using the Check Syntax option in the ISE software.
Errors reported at this stage typically involve syntax issues or constructs you've used in the code.
For example, a typo in a construct or descriptive expression can trigger a syntax error. Forgetting a parenthesis or semicolon, or failing to define a signal or module used in the code, can also lead to this type of error.
However, coding errors aren’t limited to syntax issues. During synthesis, even if you’re sure your code is syntax-error-free, other errors can arise.
For instance, if you assign a signal more than once in the concurrent section, you’ll encounter a Multiple Resource Assignment error.
Similarly, errors specific to mapping and routing may arise in those respective stages.
Some of these errors might not even originate in the VHDL code itself but rather in the UCF file.
For example, if you assign a pin number in the UCF file that doesn’t exist on the selected FPGA device, an error will inform you that the specified location doesn’t exist on the chosen FPGA.
Types of Messages in ISE
When you input a hardware description code into ISE and go through the processes of checking syntax, synthesis, placement, routing, and generating the configuration file (bit file), various messages appear in the Console window at the bottom of the main screen.
These messages fall into three main categories: Info, Warnings, and Errors.
Info Messages
Info messages are notifications from ISE software to inform you about important events during implementation.
Generally, you don’t need to take any specific action regarding these messages, and the implementation process proceeds smoothly.
Warning Messages
Warnings are messages that ISE generates to prompt you to review certain aspects of your code and make adjustments if necessary.
Warnings don’t halt the implementation process.
If only warnings appear during implementation, the circuit will still complete and function as expected. However, the final outcome might differ slightly from what you originally intended.
For example, during the synthesis stage, suppose you define a signal in VHDL but leave part or all of it unused.
You might have intentionally chosen not to use this signal or simply forgotten to include it. In either case, the software issues a warning indicating that a signal in your code is unused.
You can review this warning to determine if you need to use the signal or, if it's irrelevant, ignore it.
Error Messages
Errors, however, are messages that, if encountered, will halt the implementation process.
These messages typically relate to issues that conflict with the principles of digital circuit implementation.
For instance, if you assign a signal more than once in the concurrent section, an error will occur and synthesis will stop.
When a coding error is encountered, you must resolve it to successfully and accurately implement your code.
Common VHDL Coding Errors
As mentioned earlier, errors can occur at any stage of the implementation process.
In this article, I’ll examine 10 common VHDL coding errors.
Error #1: Missing Semicolon, Parenthesis, or Part of a Construct
Error Message: ERROR: HDLCompiler:806 – "D:\Project\example.vhd" Line 77: Syntax error near "if".
Message Description: This message identifies the VHDL file or module with the error and the line where it occurred. The error title is Syntax error near W, where W represents a keyword near the error. In the example above, the error is near the if statement.
Stage: Check Syntax - Compile
Cause: This error arises from forgetting to type a parenthesis, comma, semicolon, or a part of a structure in the code. For example, in an if-then-else structure, omitting the then statement can cause this issue.
How to Fix: This error may not always appear on the exact line indicated. Check around the specified line to locate and resolve the issue.
Error #2: Using an Undeclared Signal
Error Message: ERROR: HDLCompiler:69 – "D:\Project\example.vhd" Line 43: <my_signal> is not declared.
Message Description: This message shows the VHDL file or module and the exact line with the issue. The phrase <my_signal> is not declared indicates that my_signal is used in the code but hasn’t been defined.
Stage: Check Syntax - Compile
Cause: A signal is used in the code without being declared first.
How to Fix: First, determine the type and bit-width required for the signal. Then, declare it in the declarative region, which is before the begin statement in the architecture section.
Error #3: Uncalled Package
Error Message: ERROR: HDLCompiler:69 – "D:\Project\example.vhd" Line 16: <unsigned> is not declared.
Message Description: This message identifies the file or module containing the error and specifies the line where it occurred. The error <unsigned> is not declared indicates a type that’s used in the code without being defined. The unsigned and signed types are found in the numeric_std package, and if you forget to include this package at the beginning of your code, this error will appear.
Stage: Check Syntax - Compile
Cause: The code uses signed or unsigned types, but the numeric_std package has not been included at the beginning of the code.
How to Fix: Add the following line at the beginning of your code to call the numeric_std package:
use ieee.numeric_std.all;
Error #4: Multi-bit Initialization of a Single-bit Signal
Error Message: ERROR: HDLCompiler:837 – "D:\Project\example.vhd" Line 26: Type std_logic does not match with a string literal.
Message Description: This message specifies the VHDL file or module and the line where the error occurs, indicating a mismatch between std_logic (a single-bit type) and a multi-bit string literal.
Stage: Check Syntax - Compile
Cause: Assigning a multi-bit value to a signal defined as a single bit.
How to Fix: Assign a single-bit value to the single-bit signal to correct this issue. For instance:
signal my_signal : std_logic := '0';
Error #5: Assigning a Signal to a Signal of a Different Type
Error Message: ERROR: HDLCompiler:1728 – "D:\Project\example.vhd" Line 83: Type error near my_signal; current type unsigned; expected type signed.
Message Description: This message shows the file or module and the line where the error occurred, noting a type mismatch between my_signal and the expected type.
Stage: Check Syntax - Compile
Cause: This error arises when you attempt to connect a signed signal to an unsigned one, or vice versa.
How to Fix: Depending on the requirements of your design, use type conversion or redefine the signal with the appropriate type.
Error #6: Assigning a Signal to a Signal of a Different Bit Width
Error Message: ERROR: HDLCompiler:410 – "D:\Project\example.vhd" Line 88: Expression has 8 elements; expected 3.
Message Description: This message indicates the file or module and line where the error occurred, showing a mismatch in bit width. Here, the right-hand signal has 8 bits, while the left-hand signal expects only 3.
Stage: Synthesis
Cause: This error occurs when you assign a signal with a different bit width to another signal.
How to Fix: Depending on your design, you may need to use a bit-width conversion function (such as resize) or redefine the signal with the correct bit width.
Error #7: Missing when others Clause in a CASE Statement
Error Message: ERROR: HDLCompiler:299 – "D:\Project\example.vhd" Line 79: case statement does not cover all choices. 'others' clause is needed.
Message Description: This message specifies the VHDL file or module and line where the error occurs, indicating that the case statement doesn’t cover all possible conditions. The when others clause is necessary to handle any unspecified cases.
Stage: Synthesis
Cause: In VHDL, all possible conditions in a case statement must be accounted for. Since it’s often impractical to list every possible case, the when others clause serves as a catch-all for any remaining conditions. This error arises when the when others clause is missing from the case structure.
How to Fix: Add the when others clause as the final condition in the case statement.
Error #8: Multiple Assignments in the Concurrent Section
Error Message: ERROR: HDLCompiler:1401 – "D:\Project\example.vhd" Line 68: Signal my_signal in unit my_module is connected to multiple drivers.
Message Description: This message identifies the file or module, the signal, and the line with the error, noting that my_signal is being assigned multiple drivers in the concurrent section of my_module.
Stage: Synthesis
Cause: In VHDL, a signal may be assigned multiple times in a Process statement but only once in the concurrent section. If this rule is broken, or if a signal assigned in a Process is also assigned in the concurrent section, this error occurs.
How to Fix: Review your code and ensure that the signal is assigned in either the concurrent section or the Process statement, but not both. Only one assignment should occur in the concurrent section.
Error #9: Connecting a Port to a Non-Existent FPGA Pin
Error Message: ERROR: MapLib:30 – LOC constraint P200 on my_port is invalid: No such site on the device.
Message Description: This message indicates that the specified port, my_port, has been mapped to a pin (P200) that doesn’t exist on the chosen FPGA device.
Stage: Map
Cause: In ISE, pin assignments are made in the UCF file, specifying which FPGA pins connect to the module’s ports. If an incorrect pin number is used, such as one not available on the FPGA, this error occurs.
How to Fix: Check the FPGA and board documentation to find the correct pin number and update the UCF file accordingly.
Error #10: Undriven Output Port
Error Message: ERROR: PhysDesignRules:368 – The signal <my_signal_OBUF> is incomplete.
Message Description: This message shows that the output port, <my_signal_OBUF>, has not been connected to any signal or source.
Stage: Bit File Generation
Cause: In VHDL and within ISE, an output port defined in an entity must be connected to a signal or assigned a value. If an output port remains unconnected, this error will appear.
How to Fix: Based on your design requirements, connect an appropriate signal to the output port.
Debugging VHDL Code - Strategy for Resolving Errors
When you first enter code into ISE, it may contain multiple errors.
Often, many errors are related, and fixing one can resolve several others.
To use this approach effectively, follow these steps:
1. Always start by addressing the FIRST error.
Errors are listed in the Console window, and since this window can be small, scroll up to locate the first error message.
Click on the red error message (which includes the file path) to jump directly to the error location in the code. A yellow triangle will mark the approximate location of the error.
2. After fixing the first error, save the file and rerun the implementation process.
This may automatically clear multiple errors at once, allowing you to move on to the next remaining error and repeat the debugging process.
3. Each time you fix an error, read the full error message and consider its meaning.
With experience, you’ll recognize patterns in error messages, helping you diagnose and fix issues faster.
The errors discussed here are just a subset of the errors you might encounter when designing digital circuits in ISE.
However, these 10 coding errors are among the most common ones you'll face.
To learn more about these and other errors, you can click on the red ERROR text in the Console window while connected to the internet.
Do you encounter errors not listed in this article? Share them with us and other readers to help broaden our understanding of VHDL coding.