The last version of the Xilinx ISE Design Suite was released by Xilinx at the end of 2013, and since then, this software hasn't been updated.
However, we still need to learn and work with this software.
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Why You Still Need Xilinx ISE in 2024
The reason is that FPGAs supported by ISE are not supported by Vivado, which is the newer software from Xilinx.
On the other hand, FPGAs supported by Vivado are not supported by ISE. For instance, the Spartan 6 FPGA, which is still officially produced by Xilinx and is widely used, is only supported by ISE.
So, if you're using this FPGA in your project, you’ll have to use ISE.
In another video, I've explained how to download and install Xilinx ISE on Windows 10 and 11.
But in this video, I want to introduce you to the Xilinx ISE Design Suite.
Introduction to Xilinx ISE Design Suite
This is the software Xilinx designed for the design and implementation of digital systems using their FPGAs.
Xilinx generally has two software tools for implementation: ISE and Vivado.
Vivado is the newer software, which they've been offering independently since late 2013.
Now, before we dive into the software, let me first introduce some of its features.
Key Features of the ISE Design Suite
Using the ISE editor, you can input your design in either VHDL or Verilog.
With the ISE simulator, called ISim, you can simulate your design.
Then, you can synthesize the design, perform placement and routing, and generate the configuration file, also known as the bit file, which I explained in previous videos.
With a feature within this software, and using an external programmer, you can program the FPGA.
Using this software, you can perform various optimizations for your design. You can even test your design while it's programmed on the FPGA using a vital feature called ChipScope.
The availability of ready-made IP cores is another feature of this software. IP cores are pre-written codes that you can use in your designs.
With ISE, you can perform various analyses on your code before final implementation. Timing analysis and power consumption analysis are among the most important of these analyses.
This software provides you with detailed reports of the synthesis, placement, routing, and simulation stages. By analyzing these reports, you can understand how closely your design matches your intended outcome.
Now, with these explanations, let's get familiar with the Xilinx ISE software environment.
Getting Started with ISE
After you've installed ISE on your computer, to run it, you select the option called Project Navigator.
Select the option Project Navigator to run ISE.
After running this program, you'll see the following screen:
Right now, no project is open. The first thing you need to do to start the implementation process is to create a project.
Creating a New Project
To create a project, you can click the New Project button on the start page or select New Project from the File menu.
To create a project, click the New Project button on the start page or select New Project from the File menu.
After selecting this, you need to choose a name for your project. I'll choose the name First_Project, for example.
Next, you need to choose the project location. I've already created a folder called XILINX_Projects on the D drive, and all the projects I create from now on will be placed in this folder.
In the next step, we need to specify which technology the project is intended for. As you know, Xilinx FPGAs come in various families, which we discussed in a previous video.
Before you start working on the design and implementation, you must specify which FPGA you intend to implement your design on. In this section, under Family, you can specify which FPGA you want to use.
I'll select the Spartan 6 FPGA because the practical examples I've planned for you in the next videos are based on this FPGA, and it's one of the two FPGAs we use in our online courses at FPGATEK.
The Spartan 6 FPGA family has various members. I'll choose the LX9.
I'll select the TQG144 package.
Then, I'll choose its Speed Grade, which is one of the FPGA's characteristics written on the chip itself. I'll select speed grade -2.
Now, in the Synthesis Tool section, I specify the software that will synthesize my code.
You might ask why we need to choose a software tool.
The reason is that some companies, which may not even manufacture FPGAs, produce software for specific design stages.
For example, specifically for synthesis, there are tools available from other companies. Or, for simulation, besides Xilinx's own simulator, ISim, there are other simulators like ModelSim from Siemens (previously developed by Mentor Graphics.)
So, if you want to choose a different synthesis tool, you can select it from the Synthesis Tool section, if you've installed it on your computer.
But we'll use the ISE software's synthesis tool, called XST -- XST stands for Xilinx Synthesis Tool.
For the simulator, we'll also use ISE's own simulator, ISim.
In the Preferred Language section, we specify whether VHDL or Verilog is our preferred language. Note that choosing one of these languages doesn't mean you must code in that language.
For example, if I choose VHDL, I can still code some modules in VHDL and some in Verilog within the same project.
So, why do we choose a language here?
The reason is that in some design stages, the software generates part of the code for us, and by specifying the preferred language, we tell the software which language to use for generating that code.
I'll choose VHDL here as well and then click Next.
Review the specifications once more, and click Finish to create our project.
Alright, the project is created, but it doesn't contain any files or designs yet.
Navigating the ISE Environment
You can always see the project location in the title bar, which is currently in the First_Project folder on the D drive, as we specified. Project files have the .xise extension.
In the ISE window, we have several panes. The small window highlighted in the figure below is the Hierarchy pane, which shows files hierarchically.
Below that, is the Processes pane, where we perform tasks like synthesis, placement, routing, bit file generation, and so on, using the options in this pane.
The larger window is the Editor, where we edit the design. The window at the bottom, called the Console, is where the software displays messages and information from the software.
Adding or Creating New Modules in ISE
To create the first file, we need to use the Hierarchy pane.
There are two scenarios: either we have pre-existing modules that we want to add to the project, or we want to create a new module or file from scratch.
If you right-click anywhere in the Hierarchy pane, two options appear: New Source and Add Source. Add Source is for adding pre-existing modules, and New Source is for creating a new module.
Adding pre-existing modules to a project or creating a new module from scratch.
Since we don't have a pre-existing module, I'll select New Source.
In the next window, you can see the types of modules that can be added to an ISE project.
Different types of modules that can be added to an ISE project.
Currently, I want to add a VHDL file, or a VHDL module, to the project. So, I'll select VHDL Module and give the module a name.
I'll name this module Adder because I want to design an adder now.
Using the New Source Wizard in ISE
Click Next. Here, I can click Next again and be faced with a blank text file. However, the ISE software, using a wizard, allows you to specify at least the entity section, or the ports section, in this step.
For example, to create a single-bit full adder, I'll probably have an input port A. Then, input port B, then Cin. Then, the output port Sum, which I'll specify as an output in the Direction column. And a port for output carry, Cout, which is also an output.
This Wizard allows you to specify the entity or ports section so the software can automatically create it.
Now, I click Next. I'll review my settings once more, and then click Finish.
You can see that in the editor, the software automatically generates part of the code for me; that part is the entity section.
Well, in VHDL, we use two dashes for comments. We can delete the default comments to make our code look cleaner.
As you can see, a file named Adder.vhd has been created because VHDL files in ISE are saved with the .vhd extension.
The entity is also named Adder, matching the file name. In VHDL, it’s a good practice to keep the entity name the same as the file name.
As you can see, the ports have been defined, with their modes set to input or output and their types specified as std_logic.
Here, you can also see the Architecture section, and after the begin statement, we can start writing our HDL code.
For example, for the Sum and Cout outputs, we can write:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end Adder; architecture Behavioral of Adder is begin Sum <= A xor B xor Cin; Cout <= (A and B) or (A and Cin); end Behavioral;
This is our first VHDL code for a full adder. I'm not going to dive too deep into VHDL here, as the focus is more on getting familiar with ISE.
Once the code is written, we save it.
Synthesizing and Implementing Your Design
In Hierarchy section, you see the files associated with this project. We currently only have one file, Adder.vhd.
By clicking on the Adder file, we can view the available actions in the bottom window, such as synthesizing the code.
If I want to synthesize this code, I can click on the Synthesize - XST option, and the synthesis process will begin.
The synthesis results and reports will be displayed in the Console window. These reports are also saved in a file, so you can access them later.
Then, you can perform placement and routing by clicking on Implement Design, and finally, by selecting Generate Programming File, you can generate the configuration file or the bit file.
Depending on the complexity of your code, synthesis, placement, and routing can take a considerable amount of time. This time can sometimes reach half an hour or more.
Once the bit file is generated, you can use it to program your FPGA so that the FPGA becomes the circuit you described with your VHDL code.
Reviewing the ISE Project Folder
Now that the file is saved, let’s take a look at the folder we created for the project to see its contents.
Here you see that a folder named First_Project has been created with the name we specified for the project, and all the files are located within it.
The file marked with the ISE software icon, is our project file. By double-clicking it, you can open the project from here each time.
Well, this software has many other capabilities, which we'll discuss gradually as we talk about VHDL.
We'll also talk more about the other features of this software.
